Sparsity has become a defining feature in modern computing workloads, from scientific simulations on HPC platforms to inference and training in cutting-edge LLMs. It appears across all layers of the stack: bit-level computations, sparse data structures, irregular memory access patterns, high-level architectural design such as MoEs and dynamic routing, and system-level concerns including rack-scale deployment and scale-up/scale-out networking for massive models. Although sparsity offers enormous potential to improve computing efficiency, reduce energy consumption, and enable scalability, its integration into modern systems introduces significant architectural, algorithmic, and programming challenges. The SPICE workshop brings together the architecture, systems, HPC, and machine learning communities to explore the growing role of sparsity as a foundational tool for scaling efficiency and shaping the next generation of computing systems. By fostering collaboration among researchers, practitioners, and industry experts, the workshop will focus on (a) developing novel architectures and system techniques that exploit sparsity at multiple levels and (b) deploying sparsity-aware models effectively in real-world scientific and AI applications. The format includes keynotes from academic and industry leaders, peer-reviewed paper presentations, and interactive sessions for collaboration.

Keynote Talk

Title TBA

by Josep Torrellas

Bio

Josep Torrellas is the Thomas M. Siebel Chair in Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He is the Director of the ACE Center for Evolvable Computing (an SRC/DARPA JUMP 2.0 Center), past Co-Leader of an Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC). His research interests are multiprocessor computer architectures and parallel computing. Some of his contributions include thread-level speculation (TLS) architectures, the Bulk Multiprocessor concept, deterministic record and replay mechanisms, process variation mitigation techniques, and hardware defenses against speculative execution attacks. In addition, he has contributed to several experimental multiprocessor designs such as IBM’s PERCS Multiprocessor, Intel’s Runnemede Extreme-Scale Multiprocessor, Illinois Cedar, and Stanford DASH. Among other awards, he has received the IEEE CS Harry H. Goode Memorial Award and the IEEE CS Edward J. McCluskey Technical Achievement Award. He is an IEEE Computer Society Golden Core Member, and a Fellow of IEEE, ACM, and AAAS. He received a PhD from Stanford University.

Abstract

Abstract TBA.

Call For Papers

We invite submissions that address any aspect of sparsity in computing systems. Topics of interest include, but are not limited to:

• NEW Sparsity-aware networking, interconnects, and rack-scale deployment for large-model training and inference, including scale-up and scale-out fabrics.
• NEW Sparse retrieval, memory access, and context selection for long-context and agentic foundation models.
• NEW Runtime and scheduling frameworks for selective execution and sparse activation in multi-stage and multi-agent inference pipelines.
• Sparse inference and training techniques in LLMs and foundation models.
• MoE and dynamic routing models: performance, systems, and deployment.
• Quantization, pruning, and compression methods that induce or leverage sparsity.
• Sparsity in scientific and HPC applications.
• Architectural support for unstructured and structured sparsity.
• Compiler, runtime, and scheduling frameworks for sparse workloads.
• Benchmarks, metrics, and tools to evaluate sparse systems.
• Hardware/software co-design for sparsity-aware execution.
• Sparse acceleration in near-memory, neuromorphic, analog, edge, and low-power AI systems.
• Programming models and abstractions for sparse computing.
• Case studies of sparse systems deployed on a scale.

We welcome complete papers, early stage work, and position papers that inspire discussion and foster community building. We target a soft limit of 4 pages, formatted in double-column style, similar to the main MICRO submission. If you have any questions please feel free to reach out to Bahar Asgari [bahar at umd dot edu] or Ramyad Hadidi [rhadidi at d-matrix dot ai]

Important Info:

• Submission Deadline: September 4, 2026
• Author Notification: September 18, 2026 (before MICRO's early registration deadline).
• Workshop Date: Sunday, November 1, 2026, 1:00 PM to 5:00 PM EET.
• Submission Link: hotcrp

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