The 2nd Workshop on Sparsity, the Key Ingredient from HPC to Efficient LLMs

Co-Located with MICRO 2026, Athens, Greece

Sunday, November 1, 2026 | 1:00 PM to 5:00 PM EET | Location: InterContinental Athenaeum Athens Hotel (Omikron I)

Sparsity has become a defining feature in modern computing workloads, from scientific simulations on HPC platforms to inference and training in cutting-edge LLMs. It appears across all layers of the stack: bit-level computations, sparse data structures, irregular memory access patterns, high-level architectural design such as MoEs and dynamic routing, and system-level concerns including rack-scale deployment and scale-up/scale-out networking for massive models. Although sparsity offers enormous potential to improve computing efficiency, reduce energy consumption, and enable scalability, its integration into modern systems introduces significant architectural, algorithmic, and programming challenges. The SPICE workshop brings together the architecture, systems, HPC, and machine learning communities to explore the growing role of sparsity as a foundational tool for scaling efficiency and shaping the next generation of computing systems. By fostering collaboration among researchers, practitioners, and industry experts, the workshop will focus on (a) developing novel architectures and system techniques that exploit sparsity at multiple levels and (b) deploying sparsity-aware models effectively in real-world scientific and AI applications. The format includes keynotes from academic and industry leaders, peer-reviewed paper presentations, and interactive sessions for collaboration.

Keynote Talk

Photo of Josep Torrellas

Title TBA

by Josep Torrellas

Bio

Josep Torrellas is the Thomas M. Siebel Chair in Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He is the Director of the ACE Center for Evolvable Computing (an SRC/DARPA JUMP 2.0 Center), past Co-Leader of an Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC). His research interests are multiprocessor computer architectures and parallel computing. Some of his contributions include thread-level speculation (TLS) architectures, the Bulk Multiprocessor concept, deterministic record and replay mechanisms, process variation mitigation techniques, and hardware defenses against speculative execution attacks. In addition, he has contributed to several experimental multiprocessor designs such as IBM’s PERCS Multiprocessor, Intel’s Runnemede Extreme-Scale Multiprocessor, Illinois Cedar, and Stanford DASH. Among other awards, he has received the IEEE CS Harry H. Goode Memorial Award and the IEEE CS Edward J. McCluskey Technical Achievement Award. He is an IEEE Computer Society Golden Core Member, and a Fellow of IEEE, ACM, and AAAS. He received a PhD from Stanford University.

Abstract

Abstract TBA.

Invited Talks

Photo of Po-An Tsai

Architecture Research for DL Sparsity in the Large Model Era: Challenges and Opportunities

by Po-An Tsai

Bio

Po-An Tsai is a Principal Research Scientist at NVIDIA Research. His research spans computer architecture and systems, with a focus on the hardware–software co-design of tensor accelerators, sparse computation and model compression, memory hierarchies and data movement, and efficient large-scale LLM inference. His work has influenced the design of hardware and software systems at NVIDIA and has been recognized with IEEE Micro Top Picks selections, best-paper award/nominations at ISCA/HPCA, and a MICRO Distinguished Artifact Award. He received his S.M. and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.

Abstract

As deep learning models grow, sparsity remains an important tool for improving computational efficiency. However, large models challenge the familiar research cycle of proposing sparsity patterns, pruning and fine-tuning models, and co-designing hardware. This cycle increasingly demands resources beyond individual researchers and small teams, and findings from smaller models do not always carry over. Advances in low-precision quantization also raise the bar for sparsity to deliver additional benefits. In this talk, I will discuss these challenges and highlight three opportunities through recent work with my collaborators. First, inherent activation sparsity in large models offers opportunities to skip computation and reduce data movement without fine-tuning. I will explain how the latest NVIDIA Rubin GPU Architecture exploits these opportunities. Second, sparsity can complement quantization by handling the sparse outliers that complicate low-precision representations. Third, I will share how mixture-of-experts architectures make coarse-grained sparsity central to large-model execution while introducing challenges in load balancing, expert placement, and communication, with our publicly released expert activation profiles providing a foundation for future work. Looking forward, I will argue that future architecture research for DL sparsity should work alongside low-precision formats such as NVFP4, target sparsity inherent in models and algorithms, and extend beyond arithmetic to communication, data movement, and storage. Understanding how sparsity interacts with other efficiency techniques will be essential to turning its potential into practical benefits in the large model era.

Photo of Maryam Mehri Dehnavi

Sparse LLM Inference through Algorithm–Compiler Co-Design

by Maryam Mehri Dehnavi

Bio

Maryam Mehri Dehnavi is an Associate Professor of Computer Science and Associate Chair of Research at the University of Toronto, where she holds a Canada Research Chair in Parallel and Distributed Computing, and is a Principal Research Scientist at NVIDIA. She leads the ParaMathics group, which develops scalable numerical methods, high-performance libraries, and domain-specific languages and compilers for sparse and irregular computations on parallel, high-performance, and cloud platforms. Before joining Toronto, she was an Assistant Professor at Rutgers University and a postdoctoral researcher at MIT. She received her PhD in Electrical and Computer Engineering from McGill University, and her honors include the Ontario Early Researcher Award. She served as General Chair of PPoPP 2023 and is an Associate Editor of the Journal of Parallel and Distributed Computing.

Abstract

Sparsity offers a path to more efficient language models, but reducing the number of nonzero weights does not automatically reduce inference time. Realizing these gains requires designing pruning algorithms and compiler support together, so that patterns that preserve model quality also admit efficient GPU execution. This talk explores algorithm–compiler co-design as a way to connect these objectives. Using PATCH and STOICC as a concrete example, I will show how learning a mixture of dense and 2:4 sparse tiles creates a controllable accuracy–sparsity trade-off, while compiler representations and execution schedules translate that flexibility into hardware acceleration. The resulting system achieves up to 1.38× faster end-to-end generation and 41% lower memory use for LLaMA-2-7B. More broadly, I will discuss how designing model compression alongside the software that executes it can expand the range of sparsity patterns that are both useful to models and efficient in practice.

Program

Tentative program; all times are in EET (UTC+2) and may be subject to minor changes. Each paper presentation is 10 minutes, including Q&A.

Time Title Speaker
1:00PM – 1:10PM Opening Remarks Bahar Asgari
1:10PM – 2:10PM Keynote Talk: Title TBA Josep Torrellas

Session 1: Sparse Kernels | Session Chair: Ramyad Hadidi

2:10PM – 2:40PM Invited Talk: Title TBA Po-An Tsai
2:40PM – 2:50PM Profiler-Gated Fusion of V:N:M Sparse Tensor-Core Kernels for By-Construction Non-Regressive CNN Speedups
J. Vap, P. Kogge, R. Shehayib
TBA
2:50PM – 3:00PM SpeedSparse: Exploiting Dense General Matrix Multiplication for Practical Sparse Neural Networks
S. Alladi, A. Ros, A. Jimborean
TBA
3:00PM – 3:30PM Coffee Break

Session 2: Compression, Dataflow & Accelerators | Session Chair: Farzaneh Zokaee

3:30PM – 4:00PM Invited Talk: Sparse LLM Inference through Algorithm–Compiler Co-Design Maryam Mehri Dehnavi
4:00PM – 4:10PM Connectivity, Not Coordinates: Accelerating SpMM and High-Order Tensor Contractions via Graph Abstractions
A. Ahsaei, F. Ye, H. Zheng
TBA
4:10PM – 4:20PM Fractional-Exponent Floating-Point Numbers
T. Zhang, F. Franchetti
TBA
4:20PM – 4:30PM Cross-Layer Execution under Sparsity: Joint Exploration of Fusion Depth and Spatial Granularity
H. Falahati, A. Cristal, O. Unsal
TBA
4:30PM – 4:40PM SQuaRE: Sparsity-Quantization Resource-Efficient Optimization
N. Rohbani, M. Dehghani, H. Sarbazi-Azad, A. Cristal, O. Unsal
TBA
4:40PM – 4:50PM LATTIX: A Sparse Processing-In-Memory Accelerator for Speculative LLM Inference
S. Kang, H. Ko, H. Lee, M. Jung
TBA
4:50PM – 5:00PM Closing Remarks

Call For Papers

We invite submissions that address any aspect of sparsity in computing systems. Topics of interest include, but are not limited to:

We welcome complete papers, early stage work, and position papers that inspire discussion and foster community building. We target a soft limit of 4 pages, formatted in double-column style, similar to the main MICRO submission. If you have any questions please feel free to reach out to Bahar Asgari [bahar at umd dot edu] or Ramyad Hadidi [ramyad dot hadidi at gmail dot com]

Important Info:

FAQ:

1. How strict is the 4-page limit?

The 4-page limit is a soft guideline. Your text (excluding references) may slightly exceed 4 pages (e.g., 4.25–4.5 pages). The exact length will not affect the decision on your paper.

2. Do early-stage or position papers need to include results?

Yes. Even early-stage or position papers should include some preliminary results to support their claims. We understand these papers may not yet have a complete set of evaluation results.

3. Should I list the authors in my submission?

No. In line with the main MICRO submission guidelines, please do not include author names in your submission.

4. Can I also submit my work elsewhere?

Yes. Papers submitted to SPICE will not be published in the proceedings. You are free to publish the complete version of your work elsewhere, and you may also submit preliminary or ongoing work to SPICE.

Organizers

Co-Chairs

Bahar Asgari Assistant Professor University of Maryland, College Park (UMD)
Ramyad Hadidi Principal LLM Performance Architect Volantis Semiconductor

Organizer Committee (Alphabetical Order)

Antonino Tumeo Chief Scientist Pacific Northwest National Laboratory (PNNL)
Ben Feinberg Senior Member of Technical Staff Sandia National Laboratories
Farzaneh Zokaee System-on-Chip Architect Samsung Research America (SRA)
Olivia Hsu Assistant Professor Carnegie Mellon University (CMU)
Prashant J. Nair Associate Professor / Senior Principal Engineer UBC & d-Matrix

Program Committee (Alphabetical Order)

Anirudh Jain Tenstorrent
Anshuman Verma Microsoft
Christina Giannoula Tenure-Track Faculty Max Planck Institute for Software Systems
Gerasimos Gerogiannis Visiting Faculty Researcher Google
Zishen Wan Assistant Professor Columbia University

Student Volunteers

Helia Hosseini Publicity Chair PhD Student University of Maryland, College Park (UMD)
Johnson Umeike Submission Chair PhD Student University of Maryland, College Park (UMD)

Sponsors